As the requirements for increased density DRAM circuits have evolved, many DRAM semiconductor structures have been suggested. A common feature to those suggested structures has been an attempted minimization of the surface area required for a memory cell, as that surface area is a limiting factor in the total number of cells that can be included on a single chip.
The preferred DRAM cell, from the standpoint of minimum area, is the one transistor, one capacitor cell. As the amount of signal charge that can be stored on the capacitor is a function of its area, considerable effort has been expended in designing a larger capacitor. In this regard, the prior art has employed "trench" capacitors and various methods of interconnecting such capacitors with surface-located transistors. To further DRAM cell technology, the prior art has employed mesa-style transistors in combination with trench capacitors. Nevertheless, as cell sizes have shrunk, method for fabricating such cells with reliable transistor-to-capacitor interconnections have become increasingly demanding.
The following references are representative of the prior art.
U.S. Pat. Re. No. 32,090, reissued Mar. 4, 1986 to Jaccodine et al., entitled Silicon Integrated Circuits, discloses a DRAM in which individual cells, including an access transistor and a storage capacitor, are formed on mesas formed on a silicon chip. The cell's access transistor is formed on the top surface of a silicon mesa. One plate of the cell's storage capacitor is formed by a sidewall of the mesa and the other plate by doped polycrystalline silicon which fills grooves surrounding the mesa, isolated therefrom by a silicon dioxide layer.
U.S. Pat. No. 4,728,623, issued Mar. 1, 1988 to Lu et al., entitled Fabrication Method for Forming A Self-Aligned Contact Window and Connection In An Epitaxial Layer and Device Structures Employing The Method, describes a fabrication process for providing an epitaxial layer on a silicon substrate and over predefined insulator-capped islands to form a self-aligned contact window in the epitaxial layer. Application of the method to a three-dimensional DRAM device structure is shown, with an access transistor formed in monocrystalline silicon stacked on top of a trench capacitor. A contact window for the source-to-trench connection is formed by self-aligned lateral epitaxial growth, followed by a contact-connection formations step using either a second epitaxial growth or a CVD refill and strapping process.
U.S. Pat. No. 4,734,384, issued Mar. 29, 1988 to Tsuchiya, entitled Process For Manufacturing Semiconductor Memory Device, discloses a DRAM having a memory cell including a capacitor element, utilizing a trench or moat formed in a semiconductor substrate, and a MISFET. One of the electrodes of the capacitor element is connected to a MISFET at the sidewall of an upper end of a moat which forms the capacitor element. This electrode is connected in self-alignment with a semiconductor region, which serves as either the source or drain of the MISFET.
U.S. Pat. No. 4,751,557, issued June 14, 1988 to Sunami et al., entitled DRAM With FET Stacked Over Capacitor, teaches a semiconductor memory wherein a part of each capacitor is formed on sidewalls of an island region surrounded by a recess formed in a semiconductor substrate. The island region and other regions are electrically isolated by the recess.
U.S. Pat. No. 4,761,385, issued Aug. 2, 1988 to Pfiester, entitled Forming A Trench Capacitor, discloses a trench capacitor having increased capacitance. By means of an oxidation enhanced diffusion (OED) effect, locally outdiffused regions in the doped substrate of a semiconductor material are formed. Thus, greater capacitance is achieved for a trench capacitor of equal depth.
U.S. Pat. No. 4,791,463, issued Dec. 13, 1988 to Malhi, entitled Structure for Contacting Devices In Three Dimensional Circuitry, describes a DRAM cell which provides a one-transistor/one-capacitor DRAM cell structure. An array is shown in which the cell transistor is formed on the sidewalls of a substrate trench containing the cell capacitor. The word and bit lines cross over the trench. One capacitor plate, the transistor channel and a source region are formed in the bulk sidewall of the trench. The transistor's gate and the other plate of the capacitor are both formed in polysilicon in the trench, but are separated from each other by an oxide layer inside the trench. Signal charge is stored on the polysilicon capacitor plate by an electrical connection of the source region with the polysilicon capacitor plate.
U.S. Pat. No. 4,801,989, issued Jan. 31, 1989 to Taguchi, entitled Dynamic Random Access Memory Having Trench Capacitor With Polysilicon Lined Lower Electrode, discloses a DRAM having a trench capacitor, which includes a first conductive layer formed on all of the inner surface of the trench, except for a region adjacent to the open portion of the trench. A dielectric layer is formed on the first conductive layer in the trench and on the surface of the semiconductor substrate. A second conductive layer, of the opposite conduction type, fills in the trench. The first conductive layer, the dielectric layer, and the second conductive layer constitute a storage capacitor. A metal insulator semiconductor transistor is formed in the semiconductor substrate and has a source or drain region in contact with the second conductive layer of the capacitor through the dielectric layer.
U.S. Pat. No. 4,803,535, issued Feb. 7, 1989 to Taguchi, entitled Dynamic Random Access Memory Trench Capacitor, discloses a DRAM with a trench capacitor. It includes a semiconductor substrate, a trench formed in the substrate, an insulating layer formed on an inner surface of the trench and having a bottom opening, and a first conductive layer formed at the bottom opening and on the insulating layer. The first conductive layer is ohmically connected to the semiconductor substrate at the bottom opening. The device also includes a dielectric layer formed on the first conductive layer and a second conductive layer formed on the dielectric layer so as to fill the trench. The first conductive layer, the dielectric layer and the second conductive layer constitute a charge storage capacitor. An MIS transistor is formed in the semiconductor substrate, and the second conductive layer is ohmically connected to its source or drain region.
U.S. Pat. No. 4,820,652, issued Apr. 11, 1989 to Hayashi, entitled Manufacturing Process and Structure of Semiconductor Memory Devices, discloses a manufacturing process and structure for a DRAM, each memory cell of which comprises one transistor and one capacitor. The disclosed process comprises the steps of selectively forming an insulating layer on a semiconductor substrate, and forming a semiconductor layer on the insulating layer, the semiconductor layer being connected to the semiconductor substrate via the insulating layer. A protective layer is then formed on the semiconductor layer, and includes a window having a predetermined width at a position offset from an end of the insulating layer and forming a trench through the window, with the insulating layer and protective layer serving as masks so that the semiconductor layer is still connected to the semiconductor substrate via the end of the insulating layer. A capacitor is then formed in the trench and a transistor in the semiconductor layer. Both transistor and capacitor are connected to a region of the semiconductor substrate adjacent to a sidewall of the insulating layer.
U.S. Pat. No. 4,830,978, issued May 16, 1989 to Teng et al., entitled DRAM Cell and Method, describes a memory cell formed within a single trench. A trench is formed in the surface of a semiconductor substrate. The bottom portion of the trench is filled with polycrystalline silicon to form one plate of a storage capacitor. The substrate serves as the other plate of the capacitor. The remaining portion of the trench is then filled with an insulating material such as silicon dioxide. A pattern is then etched into the silicon dioxide which opens a portion of the sidewall and the top portion of the trench down to the polycrystalline capacitor plate. A contact is formed between the polycrystalline capacitor plate and the substrate. Dopant atoms diffuse through the contact to form a source region on a sidewall of the trench. A gate insulator is formed by oxidation and a drain is formed at the surface of the trench adjacent to the mouth of the trench. Conductive material is formed inside the upper portion of the trench, thereby connecting the upper plate of the storage capacitor to a drain region on the surface of the semiconductor substrate.
U.S. Pat. No. 4,833,516, issued May 23, 1989 to Hwang et al., entitled High Density Memory Cell Structure Having A Vertical Trench Transistor Self-Aligned With A Vertical Trench Capacitor and Fabrication Methods Therefor, describes a high density, vertical trench transistor and trench capacitor DRAM cell. The cell incorporates a semiconductor substrate and an epitaxial layer thereon including a vertical transistor disposed in a shallow trench stacked above and self-aligned with a capacitor in a deep trench. The stacked vertical transistor has a channel partly on the horizontal surface and partly along the shallow trench sidewalls. Three sidewalls of an access transistor are surrounded by thick oxide isolation and the remaining side is connected to drain and bitline contacts. The memory cell is located inside an n-well and uses the n-well and heavily-doped substrate as the capacitor counter-electrode plate. The cell storage node is the polysilicon inside the trench capacitor.
In a publication by Dhong et al., entitled "High Density Memory Cell Structure with Two Access Transistors," in IBM Technical Disclosure Bulletin, December 1988, pages 409-417, a technique is described whereby a high density DRAM cell structure incorporates a pair of access transistors and a capacitor. Typically, MOS DRAM cells, which contain one access transistor and one storage capacitor, have signal-to-noise ratio and alpha-particle induced soft error limitations. To increase the packing density, reduce the soft errors and provide higher noise immunity, the publication describes a three-dimensional DRAM structure, consisting of a pair of transistors and a capacitor.
A publication by Lu et al., entitled "Three-Deminsional Single-Crystal Dynamic RAM Cell," in the IBM Technical Disclosure Bulletin, May 1989, pages 302-305, describes a three-deminsional DRAM cell which eliminates the oxide layer between the transistor body and polysilicon inside the trench and allows a source region to have good registration to the polysilicon inside the trench.
Accordingly, it is an object of this invention to provide an improved DRAM cell exhibiting minimal semiconductor area coverage.
It is another object of this invention to provide a method of fabrication for a DRAM cell wherein the interconnection between the cell capacitor and access transistor is self-aligned during the production process.
It is still another object of this invention to provide a method for fabricating an improved DRAM cell wherein, at times during its construction, planar surfaces are exhibited, thereby enabling simplified processing steps.